Please find below the links to LEGaTO integrated software components. The initial focus is on individual integration of the LEGaTO dataflow substrates of XiTAO, Maxeler and DFiant with the OmpSs programming model. We also bundle a first integration of OmpSs tasking model with Intel SGX security framework.
Chalmers and BSC are integrating XiTAO and Nanos, two task-based runtime engines with different features and capabilities. This integration will ensure interoperability, constructive and collaborative sharing of resources between the two runtimes. Eventually, OmpSs task-graphs that require minimization of inter/intra resource interference or include energy-critical computations can be seamlessly offloaded to XiTAO, while ensuring that OmpSs and XiTAO tasks independently run on the allocated subset of the system resources.
Maxeler and BSC are investigating the use of the OmpSs task-based programming model as a frontend for Maxeler’s dataflow computing model where performance of critical computations are offloaded onto dedicated dataflow engines (DFEs). OmpSs tasks that are suitable to be mapped to dataflow kernels will be identified and the resulting dataflow accelerators will be integrated into the OmpSs runtime.
Technion, Maxeler, and BSC are working on OmpSs-DFiant integration to enable dedicated HDL-based kernels to run on various FPGA platforms offered by the LEGaTO project. To simplify integration, dedicated DFiant plugins are developed to morph DFiant kernels into existing interfaces supported by OmpSs. For Maxeler platforms the DFiant code will mimic the custom HDL blocks supported by MaxCompiler, and for VivadoHLS platforms DFiant will mimic the AXI interfaces required by Vivado. With just a few additional lines of code, DFiant users will be able to compile their designs for any LEGaTO platform.
UniNE and BSC are working on the integration of OmpSs and Intel SGX. The first integration step consists of a parallel and secure version of the matrix multiplication problem. It performs the multiplication of two matrices (A and B) into a third one (C). Parallelization is achieved using OmpSs Programming Model and security is assured by means of Intel SGX framework.